What is a RAM Bank? How is it defined?
Sebastian Wright 
I've been looking around, and I can't seem to get a solid answer on what a Memory Bank is in RAM. Some say that it's something like a channel, others like a DIMM slot, others say it's just an arbitrary and nonstandard division of memory, or it may be a subdivision of a chip, with many memory banks per chip.
I would tend to lean towards the last argument being the correct one, based on my research, but how is the size of the Bank determined? Further, how do they decide how many banks fit in a chip, and is it true that only one bank can be accessed per read/write?
If this is the case then my understanding of how the memory bus is divided among the chips must be incorrect (64 bit data bus / 8 chips = 8 bit bus to each chip, that only uses 1/8th of the entire memory bus, so why can't other chips be accessed at the same time to fill the rest of the bus?)
12 Answers
A coherent 'system' address on modern Intel CPUs is sent to the correct home agent (memory controller) by the CBo LLC slice controller to which that address is originally interleaved to. The correct home agent is selected for a address based on CBo SAD interleave rules that show it is in a DRAM address range, and the bits of the address that are used to interleave the address to the home agent are removed from the address when sent and would have been within the column part of the address; the home agent then uses the address to select the correct logical channel using TAD interleaving rules (TAD_DRAM_RULE_0 – 7 for 8 separate ranges that can be configured, which selects a logical channel in the corresponding TAD_INTERLEAVE_LIST_0); the logical channel is then converted to the correct physical channel using the CHM logical to physical one-to-one mapping register (MC_CHANNEL_MAPPER), and finally the address is converted to a channel address on that physical channel using the corresponding SAG rule (MC_SAG_CH0_0), which simply removes the bits used to interleave to the channel in the TAD DRAM rule, which would have been part of the column part of the address. The resulting address is called the channel address and is of the format:
rank[z:0], bank group[x:0], bank[1:0], row[y:0], column[9:0], offset[2:0] (y is usually 16/17; x is 0/1, 0 on x16; z is 0/1 for DDR4 UDIMMs; the offset doesn't ever get sent by the controller in a DRAM transaction)
The rank, bank group and bank address pins select a bank on the correct rank on the correct module. The Skylake CPU on the Asus GL502VM gaming laptop has 4 chip select select pins per channel, and one SO-UDIMM slot per channel, and select ranks on the SO-UDIMM, but 2 of the chip select pins are disconnected, meaning there are a maximum of 2 package ranks per SO-UDIMM using the chip select pins. Each channel also has 2 bank group select pins and 2 bank address select pins, and these select a bank on the rank. Each side of the DIMM has its own clock.
On a DDR4 DIMM, the rank constitutes the DRAM chips/dies on one side of the DIMM, or if it using 3DS 2H, 4H, and 8H stacks through-silicon vias (TSVs) then each rank is a layer in the die stacks. A 2H DIMM has 2 layers on either side (its DRAM chips are DDPs), meaning it can be 4 rank and uses 4 chip selects CS0 to CS3, this internally manifests as CS0A or CSOB, CS1A, CS1B and so on based on what half of the rank the bank lies on. A 2H can also use chip selects CS0 and CS1 to select a physical rank (package rank) and then use C0 to select the logical rank (layer) within the physical rank, rather than having a chip select for each logical rank. A 4H could use 8 logical ranks using the CS0 + C[2:0] scheme (CS0 selects the module (single package rank) and C0 is on CS2; C1 is on CS3; and C2 is on NC and are used to send a Chip ID). Theoretically, DDR4 allows up to 32 ranks with 4 chip selects selecting package ranks and 8 logical ranks each. CS2 and CS3 are not used on UDIMMs, which are typically dual rank -- I'm not sure whether UDIMMs ever use a logical Chip ID. The Cx signals only appear on RDIMMs and LRDIMMs. The GL502VM supports only the traditional DDP package, which uses CS1, CKE1, and ODT1 to control the second die on the DIMM (with CS0, CKE0 and ODT0 for the first), unlike a DIMM with a single package rank and multiple logical ranks, where C0, C1, and C2 are used as chip ID selects in conjunction with a single CS, CKE, and ODT.
A bank group selects a set of banks and the bank address selects the bank within the bank group. The bank and bank group in the above format is high-order interleaved on the row but it can be configured to be low-order interleaved on some modules.
Each bank is logically split across the DRAM chips in the rank and has a global row/column decoder per DRAM chip in the rank and row buffer (sense amplifiers) per DRAM chip in the rank. The section of the bank local to a chip consists of x . This presents as a 2D array of 2D subarrays of words. The global row/column coordinate in the 2D array is decoded using some of the row/column bits, and the actual (local) row/column coordinate in the subarray is decoded using the rest of the row/column bits, finally giving the word in the column that the chip owns. Each subarray has a local row/column decoder and storage cells connected with wordlines, bitlines, sense amplifiers, write drivers, precharge drivers. A bank is spread across the DRAM chips where each chip provides a word (x4, x8, x16) from the column (where the column constitutes 64 bits / storage cells (128 storage cells with complementary / dummy storage cells for differential sense amplifier)). Locally to the chip, the column constitutes only the word that belongs to the chip and therefore there are either 4, 8 or 16 wordlines per column locally, but 64 per rank. On x16, a column spans 4 chips as word length is 16 bits.
You have to precharge the bitlines in a bank (which will do so on all chips that contain the logical bank in parallel) before accessing a column in a different row to the one open in the same bank, which drives the bitlines for each column back to VDD/2 so that another row is ready to be opened. Before a precharge, RAS is deasserted to close the open row wordline. There doesn't need to be a 'writeback' of the row buffer (page), because upon writes, the data is written directly to the cell, and then the sense amplifier is reenabled to reflect the change on the output.
The term RAM Bank is not really a standard term, but people often use it to refer to memory modules. You know, those strips you can buy that come in various sizes of memory, are rectangular shaped and has many golden connection points and a small hole cut in between to make sure it only fits the correct memory slot.
RAM stands for: Random Access Memory, which is referred to the collection of this module. RAM is what this module contains. The term Random Access is used because not only can the memory been read, it can also been written to and erased. There is also the term ROM: Read-Only Memory, which are memory chips who's values can only be read, not written to.
The terminology for Bank, Module, Bar are things people use. Module is the official name, but both bank and bar are commonly used due to not knowing the proper terminology.
So a RAM Bank (or RAM Module) is a circuit board, containing gold connection points and RAM chips and is used in computers to temporarily remember any data on the computer, for example what the window looks like, which graphics its displaying, its all stored in RAM, in one of the RAM banks/RAM Modules.
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