I have a virtual sequencer from which I execute three transactions in parallel, each one on its corresponding sequencer. So I have something like this:

class top_vseqr extends uvm_seqr extends uvm_sequencer; type_a_seqr seqr_a; type_b_seqr seqr_b; type_c_seqr seqr_c;
...
endclass: top_vseqr
class simple_vseq extends uvm_sequence; `uvm_declare_p_sequencer(top_vseqr) type_a_seq seq_a; type_b_seq seq_b; type_c_seq seq_c; ... virtual task body(); fork `uvm_do_on(seq_a, p_sequencer.seqr_a) `uvm_do_on(seq_b, p_sequencer.seqr_b) `uvm_do_on(seq_c, p_sequencer.seqr_c) join endtask: body
endclass: simple_vseq

But now I want to be able to drive specific transactions into the virtual sequencer, depending on the test I am running. To do so, I have a class with an analysis import that is updated every time the monitor sees a transaction in the interface, and a function that returns the next transaction to be driven. So now I want to do something like the following:

class test extends uvm_test; model model_a; simple_vseq seq; top_vseqr virt_seqr; ... task run_phase(uvm_phase phase); ... seq = simple_vseq::type_id::create("seq", this); seq.seq_a = model_a.get_sequence(); seq.start(virt_seqr); ... endtask: run_phase

Digging through the UVM documentation I have seen that there is a 'uvm_send macro, but it doesn't allow you to select the sequencer to run the sequence on (i.e. I haven't seen a 'uvm_send_on or something like that). What can I do?

Thanks!

3 Answers

You can implement the contents of the uvm_do_on macro without the call to randomize() (like you showed in the second snippet) without any worries. This is anyway the suggested practice by some experts, because the sequencer/driver handshake mechanism is pretty simple. The `uvm_do* macros are not the norm, they're just there to help you out in the beginning.

I don't think there is a `uvm_send_on macro but there is a `uvm_create_on(SEQ_OR_ITEM, SEQR) macro which you can use. From the UVM documentation, this is the same as `uvm_create except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified ~SEQR~ argument. In fact, the `uvm_create macro calls `uvm_create_on macro internally by passing m_sequencer by default. You can override it using the `uvm_create_on call.

Alternatively, you could also do a set_sequencer on your sequence_item object so that it sets the m_sequencer variable.

Hope this helps.

`uvm_do_on_with may statisfis your requirement, and you can also delete rand in your packet to disable randomization or add constraint

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